The present invention relates to delay circuits and particularly to variable delay circuits for high frequency signals.
Synchronous logic circuits require that logic signals to which they respond change state at times synchronized to a clock signal. It is sometimes necessary to provide means for adjustably delaying a logic signal prior to transmission to a synchronous logic circuit in order to synchronize that signal with other logic signals produced at locations more remote from the circuit, in order to account for differences in the paths that the signals follow. When a synchronous logic circuit is implemented in an integrated circuit, it is preferable for adjustable delay circuits used therewith to be implemented within the same integrated circuit in order to avoid the cost of additional discrete components.
Tapped delay lines have been used to delay logic signals but normally these cannot be implemented within an integrated circuit. A typical delay circuit implemented in integrated circuit form utilizes a cascade of logic gates, each successive gate delaying an input signal by the unit propagation time of a gate. The total delay provided by such a delay circuit is the product of the number of gates in cascade and the unit propagation time. The total delay can then be adjusted by switching logic gates in or out of the cascade. While such delay circuits are capable of adjusting signal delay over a wide range the delay resolution is limited to the propagation time of one logic gate. State changes in a data signal should occur within a narrow time window during each period of a synchronizing clock, and therefore such state changes must be synchronized with a resolution somewhat finer than the period of the clock. However, in a high speed synchronous logic circuit, the propagation time of logic gates may not be much less than the period of the clock signal controlling the circuit, and therefore delay circuits utilizing logic gate cascades may not be suitable.